Possible bug in counteren CSRs

(Luke Nelson) #1

Hi! I am running some tests on the HiFive Unleashed board to check whether certain features behave according to the RISC-V spec and Spike and came across some unexpected behavior that seems like a bug in the CPU.

The mcounteren and scounteren CSRs control which performance counter registers supervisor and user mode are able to access, respectively. These CSRs are required to be implemented if S and U mode are implemented. My test writes 0 to both of these registers in machine mode, then runs a small test case in supervisor mode that performs a rdcycle instruction followed by ecall. My expectation is that this will cause an illegal instruction exception to be triggered as per the spec. On Spike and QEMU I observe the correct behavior, but on HiFive Unleashed the rdcycle instruction succeeds regardless of the value of mcounteren.

Any ideas what could be causing this? As a sanity check I made sure that reading mcounteren back after writing it returns the expected value, which leads me to think that the hardware is simply ignoring this register.


– Luke

(Jim Wilson) #2

It is a known errata found after the FU540 docs were published. We are working to update the documentation with new errata.