Read_csrs/rdcycle on RV32IM

I use the RV32IM on Microsemi FPGA. rdcycle() or read_csr(mcycle) instructions always trap. Are they supported?

rdcycle is a U-mode instruction and is not supported by the M-Mode only cores. It can be emulated in M-Mode software.

rdmcycle should work, but the RV32IM distributed by Microsemi implements version 1.9 of the Priviledged ISA, and mcycle CSR moved between 1.9 and 1.9.1. It used to be at 0xF00 and moved to 0xB00. You may need to compile your software with an older version of encoding.h.

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Hi Megan,

I am also having this issue currently - I am trying to implement the Dhrystone benchmark for a microsemi PolarFire FPGA that is using a RISC-V architecture. I am using softconsole as the editor and whenever I hit the read_csr(mcycle) the instruction enters a trap and the register UI in SoftConsole for the mcycle CSR reads 0x0.

Do you know how I could enable reading from CSRs in softconsole? I wrote a longer description of this problem before I found this post here on stack overflow: https://stackoverflow.com/questions/64378579/how-do-i-enable-abstract-command-reads-from-csrs-in-softconsole-risc-v

I have also tried to use rdmcycle instead just to see if I could get data that way, but it seems to trap as well.

Hi Katie.

Are you doing bare metal development, not using the Linux that comes preloaded on the Icicle board?

Is your program running in Machine mode, Supervisor mode, or User mode?

Do you know which CPU core you are running on? Note that Core 0 uses a different ISA (RV64IMAC) to the other cores, though this shouldn’t affect this.

Are you running the code normally, or single stepping in a debugger? Single step can make some kinds of instructions fail depending on how the debugger is implemented.

Hi Bruce,

I am using bare metal development on the MPF3003 Polarfire board, it’s running in machine mode, and core 0 since there’s only one hart because I am using the MIV_RV32IMA_L1_AXI V2.1 architecture for the processor.

I am using a single step debugger but I have also tried to just run the entire program and it continues to trap when I try to read or write to the mcycle csr.

I have also tried to read this register using this inline c code but it traps at this as well:
uint32_t regs;
asm volatile (“csrr %0, mcycle”
: “=r” (regs) /* output : register /
: /
input : none /
: /
clobbers: none */);

If you have any other thoughts I would appreciate it!

Oh, you’re using a soft core.

It seems v2 of MIV_RV32IMA_L1_AXI switched to using RISC-V priv spec 1.10, so mcycle should be correct if that core implements CSRs.

One thing I found in a manual for it: (
https://www.microsemi.com/document-portal/doc_download/1243780-mi-v-rv32ima-l1-axi-handbook)

10 Known Issues
10.1 Reset/Power Cycle the Target Hardware before each Debug Session
At the moment, the debugger cannot effect a suitable Mi-V RISC-V CPU/SoC reset at the start of
each debug session so one debug session may be impacted by what went before – e.g. a previous
debug session leaves the CPU in an ISR and a subsequent debug session does not behave as
expected because of this. To mitigate this problem, it is recommended that the target
hardware/board is power cycled or otherwise reset before each new debug session.