My rocketchip core is rv32imac, recently I tried to use rdtime in c language.
__asm__ __volatile__ ( "rdtime %0" : "=r" (n));
But during simulation, I got an exception.
Is the rocketchip supported to use time csr register.
Our cores don’t include a timer. The timer is off core in the memory mapped I/O space. So rdtime generates an exception, and the exception handler reads the appropriate memory mapped I/O location, which may vary depending on the chip. It is simpler and faster to just directly read the timer from the appropriate address if you are in machine mode.
I don’t know if this is documented for rocketchip, but the SiFive chip documentation has a chapter that talks about the real time clock and how to access it. There is probably an interrupt handler for this in freedom-e-sdk.
The “rdtime” is defined as “read_csr(time)”. The risc-v has a time csr register, So I want to get the value of that, But I got a exception.
Yes, the RISC-V architecture specifies a time csr, but hardware is not required to implement it. Hardware is allowed to take a trap and use an exception handler to provide the time value. This is what rocket chip and SiFive parts do. Almost all CSRs are optional, and all hardware only implement a subset of them.
I have solved the problem. The time csr register is used in user mode. My rocket-chip core is rv32imac, which has a mcycle csr register rather than cycle csr register.