I am currently benchmarking the HiFive1 Rev B with the TACLe benchmark collection. For measuring the performance I use the Hardware Performance Monitor (HPM) interface. This provides easy access to clock cycles, retired instructions and a couple of extra counters that can be activated.
For my benchmarking I set the instruction cache miss event on the mhpmevent3 register and successfully receive values from the mhpmcounter3 after each benchmark run. However if cache misses occured the values I get from the mhpmcounter3 register are humongous.
clock cycle counter: 139104
instruction retired counter: 3859
instruction cache miss counter: 292057776196
I know that the huge difference between clock cycle counter and retired instructions is due to the instructions being read from flash storage. There was no cache warmup in this case.
What I would like to know is the unit or meaning of the instruction cache miss counter. The FE310-G002 manual doesn’t provide sufficient information about this. So this is perhaps some kind of common knowledge I don’t have yet…?
Thanks in advance.