Whenever LR/SC instructions are called on core 0 of u54, access violation (0x7) exception is generated. Destination address is in RAM (0x8000000 - ) . Other cores 1-4 can call lr/sc instruction without generating an exception.
Is there something I need to enable for core 0 to be able to run lr/sc?
Core 0 implements the A extension, but it is not supported for DRAM addresses.
Refer FU540 manual p17:
“The E51 core supports the RISC‑V standard Atomic (A) extension on the DTIM and the peripheral memory region. Atomic memory operations to regions that do not support them generate an
access exception precisely at the core.”
“The load-reserved and store-conditional instructions are only supported on cached regions,
hence generate an access exception on DTIM and other uncached memory regions.”
The E51 core does not have a Dcache.
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Thank you for the reply.
Why was this design decision made only for core 0 not to have Dcache? Is it for something like power concerns or something else?
You’d have to ask SiFive, but I expect it is because that core is intended for real-time tasks, where a DTIM provides predictability that cache would not.
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