U54 core on Arty 7 & S MODE

Archive RISC-V
1

Hi All,

I’m developing a own OS on arty 7 100T with the bitstream from sifive_coreip_U54_AXI4_rtl_eval_v19_08p0p1.
I’ve ran in a problem I have no idea yet how to debug. When switching from machine mode to system mode the core generates a Instruction Fault exception(mcause = 1) I tried the opensbi in a similar setup but the result seems to be the same, after I setup mepc & mstatus for the S mode, I execute a mreturn to the system start code but the it always generates a access fault on the first instruction. This happens with the MMU on or off.

For whatever is worth the qemu with machine set to sifive_u works fine.

Considering that I’m a newbie in RISCV I assume I’m not setting up something properly but I have no idea what that might be? Does anybody have any insight?

Thanks

2

To answer my own question it, while the RISCv specs don’t mention it explicitly - if the PMP is present it must be configured. Since M mode ignores the PMP protections my situation made sense.

qemu doesn’t implement this behaviour.

3

Yes, if no entry is found in the PMP for an address then machine mode = ok, any other mode = access fault.

M mode doesn’t exactly ignore the PMP as you can explicitly lock off an address range even from M mode (until full reset).

I’m not sure, but I think qemu may be taking a shortcut and pretending you don’t have a PMP if you did nothing to configure it.

4

Thanks for the confirmation. One more issue I’ve encountered: the VM seems to work, I can read and execute code but the first store my OS does to stack it generates a fault, however the scause = 0xF. I don’t see this documented anywhere. Is this a SiFive specific cause?

5

Again answering my question(doh) I was reading the wrong RISCv priv isa document. 0xf is exactly a store/AMO page fault.