I’m developing a own OS on arty 7 100T with the bitstream from sifive_coreip_U54_AXI4_rtl_eval_v19_08p0p1.
I’ve ran in a problem I have no idea yet how to debug. When switching from machine mode to system mode the core generates a Instruction Fault exception(mcause = 1) I tried the opensbi in a similar setup but the result seems to be the same, after I setup mepc & mstatus for the S mode, I execute a mreturn to the system start code but the it always generates a access fault on the first instruction. This happens with the MMU on or off.
For whatever is worth the qemu with machine set to sifive_u works fine.
Considering that I’m a newbie in RISCV I assume I’m not setting up something properly but I have no idea what that might be? Does anybody have any insight?