OpenOCD script

(Anton Krug) #1


I have two questions.

  1. I would like to try OpenOCD with the board, I see the ttyUSB0 and ttyUSB1 (first is jtag and second is console). Not sure what script I should use when a hifive script is used then the expected tap id doesn’t match. If the coreplex e51 arty is modified then I was able to connect with gdb to the target. Is there an official recomended way or script to do this?

  2. The unleashed is very nicely designed board, but I was surprised to see the fan and heatsink on it after seeing the statement that it should draw 1-2W. Is it still possible to have it passive cooled, or it needs to be actively cooled all the time?

(Jim Wilson) #2

I never tried using OpenOCD with the unleashed board.

I’m not a hardware guy. The first version of the board didn’t have fan support, and we managed to damage a few chips while testing their limits. If you are running at 1.5GHz and using all 4 u54 cores, then you need the fan. If you are running at 1GHz and using only 1 u54 core, you can probably get by without a fan. But if you only have one board, it is not wise to try running it without a fan. You might accidentally damage it.

(Megan A. Wachs) #3

@AntonKrug, for OpenOCD debugging of the HiFive Unleashed, you’re correct that the RISC-V spec is defined that you don’t need to tell it much other than the target is RISC-V, which is why the coreip_e51_arty.cfg pretty much works with a few tweaks:

  • As you noted, you can remove the expected_id part of the command as it’s basically ignored.
  • You also will want to remove the flash bank commands for now since the flash controller is at a different location on the HiFive Unleashed.
  • Finally, since the HiFive Unleashed is a multi-core target, you may want to include -rtos riscv to your target create line, which will allow you to debug all 5 harts as threads in one GDB session (otherwise, you will need to connect to each hart with a separate GDB session).

(Meadhbh Hamrick) #4

Hi @AntonKrug,

you may be interested to know we just added an openocd.cfg file for the unleashed board to the freedom-u-sdk repo that has exactly the changes @mwachs5 described at:


(Anton Krug) #5

There are some spare unleashed boards, but it looks more dangerous than I was expecting. I will leave the fan running at least for while :slight_smile:

(Anton Krug) #6

Thank you very much.

(Anton Krug) #7

If at the moment I don’t want to use “-rtos riscv” and I want to do the mentioned “connect to each hart with a separate GDB session”. For example if I want to connect to the second hart without using the rtos, should I add the “-coreid 1” to achieve it without rtos?

(Fahad Mubeen) #8

“-rtos riscv” does enable to connect with each hart, but I think it going to be deprecated soon. Sifive IDE gives the following warning when it’s used.

Consider using ‘-rtos hwthread’ instead of ‘-rtos riscv’ in the openocd config script. Use of “-rtos riscv” is unsupported, deprecated, and will be removed.
Use the [OpenOCD KB] button to get more information on how to use “-rtos hwthread”

To use SMP using “rtos hwthread” flag consider the following openOCD script, other cores can be added via coreid.1 following add core 0, 1 & 2.

JTAG adapter setup
adapter_khz 10000
interface ftdi
ftdi_device_desc “Dual RS232-HS”
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0008 0x001b
ftdi_layout_signal nSRST -oe 0x0020
ftdi_layout_signal LED -data 0x0020
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
target create $_TARGETNAME.1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
target create $_TARGETNAME.2 riscv -chain-position $_CHIPNAME.cpu -coreid 2
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
flash bank spi0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000
if {[ info exists pulse_srst]} {
ftdi_set_signal nSRST 0
ftdi_set_signal nSRST z
sleep 1500
flash protect 0 64 last off
echo “Ready for Remote Connections”