How to use load reserved in fe310-g002?

I am trying to understand the load-reserved instruction. To start with, tried to use it as below

    /* write 2 into ram addr 0x8001000 */
    li a0, 0x80001000;
    li t0, 2;
    sw t0, 0(a0);

    /* Load-reserved syntax for 'word' lr.w rd, (rs) */
    lr.w t1, (a0); /* t1 should read 2  right? */=> But this ** generates load access fault.(exception code 5 in mcause)**

Why it generate load access fault? How to use lr.w (load reserved) instruction properly?

Found out that the load reserved is restricted only to cached regions.

Section 8.2 (“A” Standard Extension) of the RISC-V Manual says on page 49

For LR and SC, the A extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for 64-bit words and four-byte aligned for 32-bit words). If the address is not naturally aligned, a misaligned address exception or an access exception will be generated.

Try making sure the lr.w instruction itself is aligned on a four-byte boundary (for RV32).

.balign 4
lr.w t1, (a0)