Section 8.2 (“A” Standard Extension) of the RISC-V Manual says on page 49
For LR and SC, the A extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for 64-bit words and four-byte aligned for 32-bit words). If the address is not naturally aligned, a misaligned address exception or an access exception will be generated.
Try making sure the lr.w instruction itself is aligned on a four-byte boundary (for RV32).