I noted a few things that perhaps the manual could be edited to address.
Reserved bits in registers defined by the RISC-V spec have their
read and write characteristics defined, such as WARL, WIRI, WLRL,
WPRI. But for FE310-G002 defined registers, such as those for PRCI and
SPI, the bits are just marked “reserved.” Many chips I have worked
with have said to write zero to a reserved field, and to ignore
reads. But what about here? I think the safest is to WPRI, but that
introduces some additional instructions to read the value in the
reserved bits so that they can be preserved, rather than just set
to zero. Please identify the correct treatment of reserved bits
in ALL registers.
In section 6.5, the text describing the pllf[5:0] field, there is
verbiage that says “signifying a divide ratio of 2 x (N + 1).”
Shouldn’t that be a “multiply” ratio?
Section 6.8 header identifies the register as LFALTCLK, the
alternate low-frequency clock register. But right below, the Table
15 caption calls it lfclkmux, low-frequency clock mux control and
status register. Which is preferred?
Datasheet states that highest clock tested is 320 MHz, but in the
manual, figure 2 shows a clock rate as high as 400 MHz. In the
manual’s text, section 6.6, it refers to the maximum speed of the
PLL output clock as 384 MHz. These seem a bit inconsistent.
Section 19.8, chip select mode register, should have some
behavior defined for a field value of 1, even if it is “undefined”
Section 19.10 Table 77 does not show 3 as a possible value. Should
probably show something, even if “undefined” or “reserved.”
Section 19.12 Table 81 shows the FIFO empty flag as RW. I would
think that would be RO. What effect does it have if one writes to
that bit? Is the write ignored? If so, it is not really RW.
In section 17.6, it mentions that each GPIO pin has a
software-controllable drive strength. The meaning of this and the
values are not defined in the manual. They are not in the GPIO
portion of the datasheet, they are hidden away in chapter 4 of the
datasheet. They are not really explained there, but one can
surmise what they do from the voltages and currents listed
there. Hard to find, should be some explanation in the manual,
maybe then a reference to datasheet.
In section 16.1, it describes how the rtccounthi/rtccountlo
register pair are 48 bits. But forsome reason there is a greater
than or equal sign before the 48. Is this a typo, or is it trying
to tell me something?
In section 16.3, there is discussion of setting a read-only
rtccmpip bit. However, in Table 49, the Interrupt 0 pending bit
has the name rtcip0, and is marked as read-write. Is that the same
bit? I cannot find any other mention of rtccmpip bit but in the
section 16.3 text. Also, the text refers to an rtccmp field, while
Table 50 shows the field name as rtccmp0.
In section 17.2, it is noted that some FPIO register are
asynchronously set to 0 and others are synchronously set to 0. I’m
sorry, I do not know what the difference between sync and async
set are. Should that be explained in the manual?
QSPI0 is flash-enabled, so the manual states that dir field in the
SPI fmt register should be initialized to 1. But it appears to be
0 when I read it using the debugger after a reset. In addition,
the txmark register seems to be initialized to 0, although there
is a statement that it will be set to 1 for flash-enabled SPI
controllers. Is the debugger messing with this data? Or maybe I am
mistaken about what is meant by flash-enabled.
In section 19.17, Table 87, the SPI Flash Instruction Format
Register, has no information on the legal values for the fields
cmd_proto, addr_proto, and data_proto. I am guessing that they are
the 4 common SPI modes.
P.S. OK, forget about item 12, I am of course not viewing the registers right after power-up, I am not viewing them until after the SiFive boot code has executed. Sorry.