There are some oddities in section 6 that Sifive might want to fix in the next manual version. I am still writing requirements using this section so I may find more, and apparently I need to do some experimentation to determine what is really going on here, but I thought I would let you know as soon as possible rather than waiting for me to finish dorking around here.
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In section 6.2, there are five registers shown in the PRCI address space. The last one is procmoncfg at offset 0xF0. I cannot find any other reference to this register in the manual nor in the datasheet.
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In section 6.5, table 11 shows the PLL R value as being 3 bits wide, whereas figure 3 and the text below state that it is only two bits wide.
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In table 13, it shows the plloutdivby1 field as being 6 bits wide. But in the text below it seems to describe it as a boolean value, that is, one bit, either true or false.
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In sections 6.7 and 6.8, two additional registers are described that are not in the list of PRCI registers in section 6.2: lfrosccfg (offset 0x70) and lfaltclk (offset 0x7C).
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In section 6.9, table 16, the default value of the HFROSC is stated as 13.8 MHz. But the HFROSC is nominally 72 MHz. It is then divided by hfroscdiv which according to Table 9 has a reset value of 0x4. That would result in a hfroscout of 14.4 MHz.
-Pete-