I am starting to wonder about myself. I keep finding problems in the manual, could it really have these mistakes in it?
The meaning of pllrefset is not in any table, but in section 6.5
it discusses the default settings of the pllcfg register and
states that pllrefsel defaults to 0x1, which means "input driven
from external HFXOSC oscillator. Sadly, experimentation has
established that this is inverted, Actually, pllrefsel has the
following meaning: 0 = HF oscillator, 1 = xtal oscillator. I made
sure of this by disabling the HF oscillator when I thought I was
on the crystal, and all went well. Selected the HF oscillator as
the PLL source and then turned it off, everything stopped.
Something seems to be wrong with the PLL Q value. In order to get the
divide value of 4 that I want, I need to use a value of 3 for Q, which
is supposed to give me a divide value of 8. So either Q or R is off
by a factor of 2. I suspect Q because if R were wrong, I would not
expect the PLL to work.
I wanted to see about getting good trim value for the 72 MHz oscillator,
as with the default trim it seems to be closer to 94 MHz. In the process,
I discovered problems in table 5.1, “FE310-G002 OTP Contents as
Item BOOT at OTP address 0 has value 0x7f10106f, manual says
it should contain 0x7f50106f
It is supposed to be a jump to LAST FENCE, which (according to
this same table) is at 0x000207f9. But I decode this instruction
as a jump to an offset of 0x1FF0, 0r 8176. Sure enough, at that
point one finds 0x0000_000F (fence), but then the rest of the code
disagrees. Those OTP addresses are too large if they are hex, too
small if they are decimal or octal. I stopped investigating here,
suffice it to say I have no idea where to find HFROSC_TRIM.