How to understand mstatus register in FE310-G002?

Table 17 in section 8.3.1 in FE310-G002 manual summarizes the mstatus register fields as below:

0:2 - reserved,
3 - MIE,
6:4 - reserved,
7 - MPIE,
10:8 - reserved,
12:11 - MPP.

Q1. Why higher bits are NOT mentioned here, as per spec this is to be 32bits in rv32imac right?

Q2. When I read the default values on mstatus register through gdb(hifive1-revb board with FE310-G002), I read only 16 bit values, why?

mv t0, x0;
csrr t0, mstatus;
(gdb)info register t0
t0             0x1800   6144
(gdb) info register mstatus
mstatus        0x1800   SD:0 VM:00 MXR:0 PUM:0 MPRV:0 XS:0 FS:0 MPP:3 HPP:0 SPP:0 MPIE:0 HPIE:0 SPIE:0 UPIE:0 MIE:0 HIE:0 SIE:0 UIE:0

Hi Vincent,

Only a portion of mstatus is shown in the manual because that particular section is dedicated to interrupt handling. If you check the Privileged Spec most of the upper bits aren’t supported on the FE310 because it doesn’t have MMU, Supervisor Mode or floating point support. Unimplemented bits will read 0x0.

The FE310 does support User Mode, and I do see Modify Privilege (MPRV at bit 17) programmable. Timout Wait (TW at bit 21) isn’t programmable which indicates it’s not supported. In fact when a WFI is executed from User Mode I see an illegal exception taken.


Hi Ralph,

How can I verify if Modify Privilege is programmable when I could n’t read more than 0-15 bits from msatatus?

Hi Vincent,

Have you tried setting any of the upper bits?

The csrr instructions will return 32-bits, but out of reset the MPRV will be clear so you need to set it.

We have an example of reading and writing CSRs here:

I modified that example to introduce a new variable ms3 to check what bits can be set:

    /* check setting the upper 15-bits of mstatus */
    METAL_CPU_GET_CSR(mstatus, ms1);
    ms2 = 0xFFFE0000 | ms1;
    METAL_CPU_SET_CSR(mstatus, ms2);
    METAL_CPU_GET_CSR(mstatus, ms3);
    printf ("mstatus first read = 0x%x second read = 0x%x\n", ms1, ms3);

Does this help?

HI Ralph,