In the due process of choosing a board to try writing some firmware on RISC-V core, browsed the HiFIve1 Rev B board. But could n’t find MISA CSR in FE310 manual. I know its an optional register to implement. But on a starter board, it would have been easy to read the supported extensions etc. Am I the one expecting this register? or is it least important?
I don’t have a HiFive1 Rev B, but this
suggests that misa is implemented. That list of registers comes from the core generator, so should be correct.
SiFive has invested in a doc group, and the new docs are much better than the old ones. The old FE310-G002 manual doesn’t have a section listing all implemented CSRs. But the new docs have a programmer’s model chapter that has a section that lists all defined CSRs. Unfortunately, I don’t know if there will be a new version of the FE310-G002 docs, and you can’t rely on the new E31 core docs because that will list new features not present in the older core used in the FE310-G002 ASIC.
The HiFive1 Rev B does have the misa register. I read mine just yesterday with a program written in Rust.
rust forum post
How important is MISA register?
Well if you use the riscv-openocd (https://github.com/riscv/riscv-openocd) probably very important as the current implementation seems to make extensive use of it as far as I can see: