I am using HiFive1 Rev-B to learn RISC-V. How to differentiate RISC-V concepts and HiFive1 design? I refer RISC-V instruction manuals and HiFive1’s FE310-G002 manual. When I read some thing in FE310-G002 manual, I am not sure whether it is applicable for RISC-V architecture in general or specific to FE310-G002 design. How to should I go about it?
It’s really impossible to say, because people making RISC-V CPUs are free to design them in any way they want to, depending on their goals. They only have to execute the instructions correctly.
SiFive’s FE310 and FU540 are typical of many traditional RISC processors designed for a good balance of performance and power efficiency. Single-issue, in-order, with a five stage pipeline aiming to acheive 1 instruction per clock cycle on workloads that fit into cache has been a good sweet spot for RISC processors for decades. You’ll find a lot of other RISC-V processors with the same general characteristics.
However there are other useful design points with different trade-offs. SiFive’s 2-series cores are much smaller, have shorter pipelines and no branch prediction. They sacrifice a little performance for a big saving in area and energy use, while still approaching 1 instruction per clock cycle. PULP project’s Zero-RISCY and ARM’s Cortex M make similar tradeoffs.
Some cores such as Clifford Wolf’s PicoRV32 or Olof Kindgren’s seRV sacrifice much more performance for even smaller area, especially in FPGAs.
In the other direction SiFive’s 7-series and Western Digital’s SweRV (like ARM’s A7/8/9/53/55) provide higher performance via dual-issue and slightly longer pipelines. In the future you can expect to see RISC-V processors with Out-of-Order processing, which is even higher performance, especially when there are a lot of L1 cache misses, at the cost of much higher energy use and silicon area.
In summary, the FE310 is typical of a broad range of typical RISC-V cores, but quite different characteristics are also possible.
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