Table 20: SiFive Feature Disable CSR lists
17 Disable instruction cache next-line prefetcher
There is the warning: A particular Feature Disable CSR bit is only to be used in a very limited number of situations, as detailed in the Example Usage entry in Table 21.
However, is there now more information on feature 17?
How and when is it triggered currently [if enabled]?
Is the cacheline scanned [even partially as the last instructions loaded by fetch] to determine if fall through is possible?