Hello,
I have recently acquired the Unmatched RevB platform and I have started making some baremetal tests. While executing the Dhrystone benchmark on the U7 core, I noticed that the score was smaller than the one it should be. Using the performance counters I saw that the “Data cache/DTIM busy” was always zero (“Instruction cache/ITIM busy” wasn’t zero). At this point, my hypothesis is that the data is not being cached. Looking at “Table 23: U74-MC Core Complex Memory Map” of the U74 TRM, I see that the only memory with the cacheable attribute is the DDR SDRAM. Therefore, I am now placing the data in this memory instead of using the default behavior which is to put it on the L2 SRAM. However, the dhrystone score is now worse, meaning that data is still not cached and that it is being searched in the main memory.
Due to my lack of knowledge on both, RISC-V and SiFive, I am not sure what could be my problem. I have tried to see if I needed to activate the data cache as happens in ARM for example, but it seems that it is always active according to the manual. I have tried executing in supervisor mode in case machine mode supposed a problem somehow but the “Data cache/DTIM busy” is always zero. The only thing that I have not tested yet is the MMU which is disabled (VA = PA according to documentation). It seems that there is no attribute related to the caching of the data in the PTE configuration bits. I have neglected this possibility, but could this be the problem? Or is it something simpler that I am missing?
I would appreciate any advice or direction I could follow.
Thank you for your time!