I want to do some rowhammer test, is there any method to close the cache?
See the FU740 docs on the web site.
The L1 data cache can’t be disabled.
The L2 has multiple ways (16?) which can be configured as cache or scratch pad memory. However, there must always be at least one way configured as cache, so you can only decrease L2 to 1/16 of the normal size this way. Also, you can’t decrease cache at run-time, you can only increase it. It comes up from reset with 1 way enabled, and then u-boot enables all of the ways. You could hack u-boot to stop enabling all of the ways. This would be arch/riscv/cpu/fu740/cache.c in the cache_enable_ways function.
I’m not an expert in this area, so I might not have gotten all of the details correct. See the docs and the u-boot source code.
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Thanks for your reply.
If I don’t open the L2 cache ways at the boot process of u-boot and treat the last one-way cache as L2 scratchpad, does it mean I close the L2 entirely? But at the same time, the L1 data cache always works, I still can’t do the rowhammer test, right?
I’m not an expert in this area. I know what rowhammer is, but don’t know how caches affect it. You can’t entirely close L2 cache, you can only disable 15/16 (?) of it.
If the presence of L2 cache somehow prevents rowhammer attacks then isn’t that a good thing?
But I suspect it doesn’t or x86 machines wouldn’t be vulnerable in the first place.
Some ISAs allow you to specify cache/temporal hints in load/store instructions. RISC-V doesn’t have this yet, but I believe there is a proposed extension for this. Until this gets specified and implemented, there may not be a way to completely disable caches on SiFive parts with cache.
Or maybe there is a way to disable caching in page table entries on some ISAs?
Anyways, this is outside my expertise.