I’m currently working on a U54-MC architecture (PolarFire SoC) and I’m trying to measure the impact (in terms of clock cycles) of a cache invalidate and/or flush for the L1/L2 caches.
From what I understand, for the L1 cache :
- iCache invalidate : Use FENCE.I instruction (what about CFLUSH.I.L1, what is the difference?)
- dCache invalidate/flush : Use CFLUSH.D.L1/CFLUSH.D.L1 instructions
For L2-Cache, apparently the only way to flush the L2 is done by using the Flush32/Flush64 registers of the L2 controller and writting “virtual addresses”.
Is there no way to flush the L2-Cache using set/way?
How can I flush the entire L2 Cache with these registers?
Does it mean I have to write all possible addresses present in cache to be sure the cache is 100% flushed?
(Like, if I have 2GB of DDR and each cache block is 64 bytes, I need to loop through 2048x1024x1024/64 addresses?)
Am I missing something?
Let me know if anything I’ve written is incorrect.