Configuring DRAM on the Unmatched

I am writing a primary bootloader to boot the Unmatched.

The RISC-V fu740 manual does not appear to document the DDR controller and PHY Control register options very extensively (section 23.2.2, p.198)–I am sure there are too many options.

Thinking I could clone known good settings for the Unmatched board, I have a copy of u-boot and the Freedom SDK source, but cannot find in these repos where SiFive sets these registers on boot for the Unmatched. If anyone knows the proper settings for the Unmatched board, or where I can find them documented or implemented in source, I’d very much appreciate it. (I am working on Step 3 of section 23.3 on page 200.)

It looks like the dirty work is done in u-boot/drivers/ram/sifive/sifive_ddr.c. It loads a big table from u-boot/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi that has the register values.

I’ll guess you’ll need an NDA from SiFive to get the documentation for all 1480 of those registers.

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Not from SiFive but from Cadence I think.

Yeah, Cadence for sure. In the code, the registers are named DENALI_CTL_xxx and DENALI_PHY_xxx.

Thank you so much, guys. I wouldn’t have found this the way I was searching through the code (wasn’t even thinking to look for data tables). Thanks so much; this will be helpful.