I am PhD student of computer engineering. I am working to build a CGRA accelerator for RISCV. I have done the CGRA accelerator for MIPS32 and ARM7. Now I am switching to RISC-V. I have downloaded lots of RISC-V cores from github and other places. Some of them have bug. Some of them are incomplete. Some of them are written with non HDL languages (VHDL, Verilog). Finally I download S21 and some others from SIFIVE. But this code is not fully RTL. It is something between RTL and netlist and is not readable and understandable codes.
It is my story in these two weeks!!!
Is there any bug free HDL codes for RV32I or RV64I in github or sifive or any other places?
Help me please