Hello There,
I’m an online course developer (MOOC’s). I just wanted to design an extensive course on SiFive cores. So just downloaded one version of SiFive core to understand. But I saw a note that for non licensed access, the core is made intentionally confusing. Is that the case ? . I just wanted to understand more about your implementation & to make a course on them. Is that not possible without license ?
Regards,
Bivin
I’m not one of the hardware designers, but
https://github.com/sifive/freedom
has the sources for our free cores.
You can find a list of other free cores here
https://riscv.org/risc-v-cores/
Thanks for your inputs @jimw
Do we also get the complete RTL source for the FE310-G002 microcontroller ?
Thanks.
Regards
Vinoth
FE310-G002 is an asic. You can’t get rtl for an asic. An asic is a lot more than rtl. You can get rtl for a core if you license it. We have rtl for eval cores that is obfuscated. Or you can get source for cores from the freedom repo as already mentioned. The fe310 is essentially the same as the freedom repo for the RISC-V core, plus some extra modules to complete the asic, some of which may be licensed, run through commercial tools to generate the asic.
As already mentioned, I’m not a hardware guy, so I don’t know the details. Other than the fact that the freedom repo is what you want.