The E3 Coreplex manual mentions that the E31 core can have an instruction RAM (instead of an instruction cache) and a data RAM (instead of a data cache). However, in the memory map chapter (chapter 4), I cannot find the address range for the instruction RAM & the data RAM. I assume that they are not located in the RAM area through the AXI memory interface. Are they located in the “On-Coreplex Devices” area? And how are the base addresses of these two RAMs determined?
The instruction and data RAMs are mapped adjacently into the RAM area, at 0x8000_0000 and above. As you inferred, these memories are tightly coupled to the pipeline and are not accessed over an AXI interface. The next version of the E3 Coreplex manual will describe that RAM region more generically.