DDR RAM addition to E300 on Arty


(Salman Sheikh) #1

I attempted to modify the scala files to create an E300 Arty board with the DDR. I don’t fully understand scala, chisel, et al but tried to copy what someone else did on these forums for the Nexys4 board with DDR. I got this address map below after running the make -f verilog. Would the DDR be shown in the generated Address Map if it got built into the verilog?

Generated Address Map
0 - 1000 ARWX debug-controller@0
10000 - 12000 R XC rom@10000
2000000 - 2010000 ARW clint@2000000
c000000 - 10000000 ARW interrupt-controller@c000000
10000000 - 10001000 ARW aon@10000000
10012000 - 10013000 ARW gpio@10012000
10013000 - 10014000 ARW serial@10013000
10014000 - 10015000 ARW spi@10014000
10015000 - 10016000 ARW pwm@10015000
10016000 - 10017000 ARW i2c@10016000
10023000 - 10024000 ARW serial@10023000
10024000 - 10025000 ARW spi@10024000
10025000 - 10026000 ARW pwm@10025000
10034000 - 10035000 ARW spi@10034000
10035000 - 10036000 ARW pwm@10035000
20000000 - 40000000 R XC spi@10014000
80000000 - 80004000 ARWX dtim@80000000