I-Cache, D-Cache Confusion

I am trying to understand the Freedom E300 Arty implementation. It is not completely clear to me what is similar and what different between E31 Coreplex and the fpga implementation. According to several sources E31 has 16kB I-Cache and 16kB DTIM. The default configuration of the Arty implementation shows me following utilization: I-Cache: 1xRAMB36 (1k x 32) and DCacheDataArray: 4xRAMB36 (4x 4k x 8)
After reading different sources I am completely confused what is D-Cache, Data-SRAM or DTIM. I read that E31 does not have D-Cache, but I can see a dcache block in Vivado.

Could somebody help me to clarify. I appreciate every bit of help, since I need this for my master thesis

Thank you in advance

@HEX-Five has released a modified E300 (X300) implementation that tries to match the E31 specs w.r.t. to caches and memory - https://github.com/hex-five/multizone-fpga. The extracted E300 specs and the modifications are listed in the README.md. Hope it’s useful.