The specs page says RV32IMAC. 16 KB SRAM, 16 KB 2-way associative instruction cache. 128 Mbit (16 MB) flash. Great.
It says the flash is SPI. So it’s only available for serial access? Or hardware transparently maps it into the address space? I see 0x20000000 - 0x7FFFFFFF is reserved by E31 for such purposes.
Is User Mode (and MMU) implemented?
What does the instruction cache cache? i.e. where is it loaded from on a cache miss? E31 Coreplex manual says the optional data/instruction caches reload from the TileLink. So … from the flash memory, then?