Hi All, Following up on this there are 2 issues related to our SPI controller:
Issue: The output enable signal for DQ is not driven properly.
Devices affected: FE310-G000, FPGA bit files we made available before 5/2
Symptoms: Address and write data using DQ for transmission will not
function properly. Reads using DQ are unaffected.
Do not use opcode 0xEB in the Extended SPI protocol. In some devices, this
command is also referred to as QUAD INPUT/OUTPUT FAST READ.
Do not use the Native Quad SPI Protocol. In some devices, this command is
also referred to as FAST READ.
Issue: Certain frame lengths do not work properly.
Device affected: FE310-G000, FPGA bit files we made available before 5/2
Symptoms: Certain frame lengths do not work, and will result in the master
sending one extra clock pulse. The slave device may then become out of
The following frame lengths are supported and can be used. Do not use
other frame lengths.
- Serial: 0, 2, 4, 6, 8
- Dual: 0, 1, 3, 5, 7, 8
- Quad: 0, 1, 2, 3, 5, 6, 7, 8
These will be officially documented as errata in future documentation related to the FE310-G000. The FPGA bitstreams will be updated with new versions of the SPI controller soon.
Thanks again for reporting this.