Maximum Flash Size of Off-Chip QSPI Flash

Hi, I want to know if the Freedom E310-G000 SoC can support more than 128Megabits of Flash. I read the memory map and it suggested that 512MiB (I think Mebibyte) of flash is supported). That would be nearly 4Gbit. Is this really possible? Or is my math wrong?
If so, is there any other reason except cost, why a 128Mbit chosen?

Flash chips larger than 16MiB require an alternative read command (4-byte addressing) to use. On power-on the chip does not use these commands. However, once booted, you can certainly use larger flash chips through the memory map, up to 512MiB (if such chips exist). Indeed, if you want to use the SPI controller directly (not through the memory map) there is no limit to how large a SPI flash chip you could support.

As for why it has the flash chip it has, we had to pick a part and that’s the one we picked. A PC can hypothetically support a >16TB hard disk, but they don’t exist yet. Even then, most just have a ‘big enough’ disk. The same reasoning applies here.

So even if I use an QSPI flash of such ginormous proportions (if it exists), then I could access it only after booting. There are 512Mbit flash chips available and I was wondering if I could use them instead. But I guess then XIP will only work after booting.

Well, the bigger flash chips support both 3-byte and 4-byte addressing. So you can probably still use the first 16MiB of the chip on power-on. You would just need to adjust the command used by the controller before it can access beyond this limit.

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Thanks. I’m clear now.

On a related note, can the ROM-targeted QSPI channel also support reads? I have been toying with the idea of using a 4Mbit SPI F-RAM (eg: MB85RQ4ML) for XIP code and data.

Yes, it is memory mapped as RX memory.