Hi,
How to (configure) cache FLASH memory into cache line for read (from FLASH) in hifive1-revb? FE310 manual has only a short paragraph about the Instruction & data cache and it dont discuss on configuring and enabling the cache.
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Is this perhaps of any use?
hmm, may be I asked the wrong question. FE310 (hifive1 rev B) memory map has 0x0800_0000 to 0x0B00_1fff. HOw is this E31 ITIM used/configured?
From the link above, The ICache caches pretty much caches everything – Data Scratchpad, SPI Flash, OTP Memory, Mask ROM, Gate ROM, even Debug RAM and ROM Is this true? if so where are teh configuration registers for this ?
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From the link above, The ICache caches pretty much caches everything – Data Scratchpad, SPI Flash, OTP Memory, Mask ROM, Gate ROM, even Debug RAM and ROM Is this true?
I think so. Isn’t that what the E310 documentation says?
if so where are teh configuration registers for this ?
Documentation on this seems very thin on the ground or, at least, very difficult to find. Maybe if you start here and browse the rest of the sources you can figure it out?
Great to see you again Ben @bsvtgc
Might be able to get some idea how the ICache is set up from looking at its implementation in the ICache.scala file. It’s designed to handle bursts up to 32 bytes in length, and supports XIP (execute-in-place) from an SPI peripheral.