Hifive1 revb WiFi


#1

Hi,
Are there any examples available using the WiFi of the ESP? The goal is that the HiFive fetches some sensor values, passes them to the ESP and the ESP sends them over WiFi to some service.

I tried to flash a program to the ESP (ACM0 is FE310, ACM1 should be ESP) but the serial connection failed. Which baudrate should I use? I tried the default (9600, 115200, …) but no success.
BR
who


#2

Anyone knows an answer to this? I’d also like to use the WIFI.


#3

The easiest way seems to be by using its “AT” command set. I found the spec for that here. The ESP32 chip is on one of the FE310’s three SPI buses so I need to find which one, and which is its ‘device select’ pin and some examples of dealing with it.

I note that the link to the Expressif AT information at github given in the “Getting Started Guide” is invalid. There is some info on using SPI with the ESP32 here.


#4

Cool, I’ve came to similar conclusions yesterday, except I only found out SPI is used from the schematic PDF. The guide you link to is useful too.

Like you I’m not sure how to set the SPI GPIO pins into “talk to ESP32” mode. Are you aiming for using C? I’m trying to get this working with rust/embedded-hal crates.

Also the original revB bootloader seems to set some AT commands (at least I get them on the serial terminal) to reset the wifi/bluetooth. I suspect it might be worth reverse engineering that as well since sadly we don’t have the sources to it.


#5

And I do not think it is necessary (or desirable) to flash the ESP32 with new microcode. According to the Getting Started Guide for Rev B, it is flashed at the factory with the AT support code. (See page 8) Make sure you are looking at the Rev B guide, because that is the one that talks about the ESP32 chip.

I am doing this in Mecrisp FORTH. There are three sets of SPI control registers in the FE310: one is for the flash memory and the ESP32 is connect to one of the other two. So need to find out which one. Then after that, when dealing with any SPI device there is a need for a “Chip Select” signal that typically comes from a GPIO pin. We need to look at the schematic to see how this is wired up.

There was a promise of a driver in “Q2 of 2019” but I have not seen it yet.


#6

Made some progress. According to the schematic, “SPI_CS2” is the line select for the ESP32. If I understand things correctly (thanks Disasm btw.) it means that if we want to init SPI to talk to the ESP32 we should use std. GPIO pins for MOSI/MISO and CLK and use GPIO9 (identified as SS2 in revA pinout) as the CS which should “wakeup” the ESP32 on transfers/transactions.

I still need to figure out what to send to it to test this out.


#7

There is hardware support for the SPI channels, including FIFO mechanisms on input and output. I think you would want to use those, not bit-banging the GPIO pins. According to the Memory Map (Chapter 4) the SPI registers are mapped at 0x10024000 and 0x10025000 for SPI1 and SPI2.


#8

Yes this appears to already be taken care of by https://github.com/riscv-rust/e310x-hal/blob/master/src/spi.rs on the rust abstraction side.

I set the pins when creating the struct but hardware SPI is used via the registers if the pins match a known setup (in this case it’s the GPIO9 combo one).

I think all I need now is to know what to send and expect back as a basic test of this.


#9

Ok, I see that now on the schematic. The ESP32 Chip Select is GPIO9. The MOSI/MISO/SCK lines are connected to GPIO 3,4,5 so it is SPI1 (base address 0x10024000) is the one to use.

Looking at the ESP32 AT command manual, it looks like a simple command of “AT” should get a response of “OK”. “AT+GMR” should return the version number. AT commands over a serial port have to end with CRLF but I dont know what the SPI interface expects. On the other hand, in addition to the SPI connect, there is also a UART serial connection between the two chips - perhaps the AT commands go over that, in which case they should be at 115200 bps.


#10

Orrr, we could just look at the Zephyr RTOS support for the HiFive1 Rev B :slight_smile: