Could the ZPU serve as a similar function as the 'ULP coprocessor' seen in ESP32?

[mofosyne]

The interesting thing about the ESP32 is that it has a co-processor that can perform measurements using ADC, temperature sensor, and external I2C sensors, while main processors are in deep sleep mode.

I also read about a tiny open source cpu with a GCC toolchain called ZPU. While slow, it doesn’t use much space or code size.

I wonder if this could serve as a suitable co-processor for a RSIC-V for power savings. Another interesting concept is “soft peripherals” like a bit-banged SPI bus, so the main cpu doesn’t have to poll etc…

Reference about ULP in ESP32: http://esp-idf.readthedocs.io/en/latest/api-guides/ulp.html

[mofosyne]

Example of “soft peripherals” using the ULP in ESP32:

• https://github.com/espressif/esp-iot-solution/blob/master/examples/ulp_examples/ulp_spi
• https://github.com/espressif/esp-iot-solution/blob/master/examples/ulp_examples/ulp_i2c_bitbang
  • e.g. The ADS-1015 sensor requires 16bit values readout, which ESP32 i2c hardware cannot do.

Other potential applications of a ZPU based coprocessor:

• Low speed serial console CLI that doesn’t interfere with the main thread.
• Cryptoprocessor if secured enough: (e.g. [IEEE:5749562] Towards an Ultra Lightweight Crypto Processor)
  • Could be a very useful role if used in budget RISC-V ICs in IoT applications.
• Outputting duty cycle modulated digital signals like in IR remotes and individually addressable leds (e.g. WS2812 used in NeoPixels). Most micro controllers don’t have these peripheral.
• Watchdog?
• Data logging while sleeping

Things to consider if the ZPU is to be adopted within the RISC-V eco-system as a soft peripheral/coprocessor:

• Just like how there is a standard library used in C. Perhaps a standard library of “soft peripherals” might be a useful idea in this context as well. Would this require standardising how the ZPU is connected to the bus and how much self contained resources it have?

[mofosyne]

Interestingly the idea of soft peripherals is already in development with lowRISC, though using a stripped down Pulpino (Also a RISCV) rather than a ZPU:

• Page 5 “minion cores” http://www.lowrisc.org/downloads/lowRISC-memo-2014-001.pdf

Looks to have the advantage of sharing the same RISCV instruction set. Thus less compiler infrastructure overhead. Plus is likely to be faster than the ZPU, thus can emulate faster peripherals. These advantages likely offsets the possible silicon space savings of the ZPU anyway.

Note: PULPino is a microcontroller design from https://www.pulp-platform.org/, which is stripped down to be used as minion cores in lowRISC.