I am making a very simple RV32I CPU in verilog. No pipelining, all instructions executed immediately at the next rising edge of the clock (single cycle execution for everything).
I just want to make sure:
- Since it’s single-cycle, there is no ‘fetch-decode-execute’ stages (obviously…?)
- That means that there is no such thing as Branch Prediction, since jumps cannot be optimized beyond 1 cycle
- That also means there is no need for a RAS (Return Address Stack). It will provide no benefit.
Lastly, are there any C compilers that will work with a simple custom core like this?