Beginner Risc-V CPU Branch Prediction Q


I am making a very simple RV32I CPU in verilog. No pipelining, all instructions executed immediately at the next rising edge of the clock (single cycle execution for everything).

I just want to make sure:

  1. Since it’s single-cycle, there is no ‘fetch-decode-execute’ stages (obviously…?)
  2. That means that there is no such thing as Branch Prediction, since jumps cannot be optimized beyond 1 cycle
  3. That also means there is no need for a RAS (Return Address Stack). It will provide no benefit.

Lastly, are there any C compilers that will work with a simple custom core like this?


gcc supports -march=rv32i, or you can use the configure option --with-arch=rv32i to get a gcc build that supports rv32i by default. You will probably also need -mabi=ilp32 to specify the ABI in use, or --with-abi=ilp32 to specify it at configure time. SiFive has prebuilt compilers on its web site, or you can build your own using sources from our github sifive/freedom-tools tree, or from the RISC-V International sources in github riscv/riscv-gnu-toolchain. The latter is simpler to use.

I don’t know whether you’d be interested in looking at another core along the same lines?

As Jim says, gcc is happy to make RV32I code and will generate library calls for multiplication and division and floating point (if used). The NewLib “embedded” runtime library is also happy with this.

Looking into gcc now, thanks. Is my understanding of branch prediction and single-cycle cores correct? (No reason for it or even HINT instructions)

The code emitted by gcc will work regardless of whether you have branch prediction support, and regardless of whether you have single cycle cores or not. Neither one affects the correctness of the code. The only issue is that for best performance, you might want to optimize differently. But for a single cycle core with no branch prediction, it probably doesn’t matter how you optimize, the code will take the same amount of time to execute regardless of how the instructions are scheduled.