FU500 RV64V implementation

(John Piliounis) #1

Hello all. Great future ahead with RISC-V technology 4all of us, as it seems. Have been engaged on the RISC-V ISA a couple of months ago. Have study already the ISA specs from RISC-V home and also the books of Patterson, Hennesy, Waterman. For many years I’m working with projects on ARM32 / Cortex M4, M7 and Cortex Axx and also on .NET C# & .Net Core for Linux. Have implement many projects in CUDA also. Haven’t clarify so far if FU540 supports vector based calculations - RV32V or RV64V. Please advise.
Thank you,

(Bruce Hoult) #2

Hi John,

The FU540 does not have anything similar to AVX or NEON.

A vector processing instruction set extension is under development. The draft spec is almost done and there should be experimental hardware implementations and compiler support in the next 6 to 12 months, followed by ratification as a standard part of RISC-V.

Everyone appreciates that this is something very much in demand, but at the same time we want to do it right and learn from the missteps of other ISA vendors.

(John Piliounis) #3

Hello Bruce. Thank you very much for your reply and update.
As Patterson & Waterman state at Chapter-8 of their book, ‘The RISC-V Reader, An Open Architecture Atlas’, the RV32V extension is not only already well defined at the logical/registers/command levels but also outperforms by far the x86-32, MIPS-32 SIMD operation schemata. So we’ll all need to wait until vectorization becomes an integral part of a future SoC by SiFive.
Here is a rather complete analysis of the SIMD vs RV32V technologies.

All the best for all,