Hello all. Great future ahead with RISC-V technology 4all of us, as it seems. Have been engaged on the RISC-V ISA a couple of months ago. Have study already the ISA specs from RISC-V home and also the books of Patterson, Hennesy, Waterman. For many years I’m working with projects on ARM32 / Cortex M4, M7 and Cortex Axx and also on .NET C# & .Net Core for Linux. Have implement many projects in CUDA also. Haven’t clarify so far if FU540 supports vector based calculations - RV32V or RV64V. Please advise.
Thank you,
John
Hi John,
The FU540 does not have anything similar to AVX or NEON.
A vector processing instruction set extension is under development. The draft spec is almost done and there should be experimental hardware implementations and compiler support in the next 6 to 12 months, followed by ratification as a standard part of RISC-V.
Everyone appreciates that this is something very much in demand, but at the same time we want to do it right and learn from the missteps of other ISA vendors.
Hello Bruce. Thank you very much for your reply and update.
As Patterson & Waterman state at Chapter-8 of their book, ‘The RISC-V Reader, An Open Architecture Atlas’, the RV32V extension is not only already well defined at the logical/registers/command levels but also outperforms by far the x86-32, MIPS-32 SIMD operation schemata. So we’ll all need to wait until vectorization becomes an integral part of a future SoC by SiFive.
Here is a rather complete analysis of the SIMD vs RV32V technologies.
All the best for all,
John
Hi,
are there any news about this topic? Have been the vector processing instruction set implemented on any of SiFive cores, U54 or any other?
Thanks.
The V extension specification has not yet been fully completed, but it is close. Remaining changes are likely to be additions, rather than changes to what is already there. Hopes are to have it ratified during 2020.
During 2019 support for the draft vector specification has been added to gnu binutils, and the Spike simulator. Work is underway by various people around the world to add support to gcc and llvm compilers.
SiFive announced at the end of October that the U87 core with the Vector extension will be made available to customers in the second half of 2020.
The Vector extension is going to be important across a wide range of markets.
Hi Bruce, Thanks for the update.
Is any anticipation about the performance characteristics of U87 available? Like: number of cores, comparation with ARM, DMIPS/MHz, DMIPS/Watt …?
I believe no announcement of configuration or specifications has been made.
Once you have a Cray-like vector unit (as RVV is), Batcher’s definition applies: “A supercomputer is a device for turning compute-bound problems into I/O-bound problems.” Or more directly, into memory-bound problems. Even with quite modest vector units the question is not how many MIPS or MFLOPS you can do, but how much cache/memory bandwidth you are willing to pay for.