What is the status of the vector extension? Is there any implementation of the Cray-style vector extension in soft- or hardware available?
I think this would be more usefully asked on the RISC-V isa-dev mailing list which can be joined at https://riscv.org/mailing-lists/
In short, as I understand it, the basic style of vector extensions (Cray-like, as you say) and set of operations has been agrees on for some time. There was some resistance to the polymorphic instructions originally proposed on the grounds of being more complex to implement than some members wanted. I believe something along those lines will still happen as an optional extra extension, but the basic vector extension will now have explicit types. A first draft of the actual instruction set and proposed binary encoding was circulated a few months ago, and something like a final candidate is expected to be circulated very soon.
No interim software or hardware implementation of the proposed instruction set has been created by anyone yet, as far as I know. I believe that some will be created (emulator and at least FPGA) once the final candidate instruction set has been circulated, in order to gain practical experience before ratifying it as a RISC-V standard.