Kindly clarify the below mentioned issues:
I have searched a lot to find out that how many clock is needed for operation of each instruction in ISA RV32G variant, but I couldn’t find any thing.
Thanks in advance
The ISA does not specify the CPU cycles for each instruction. There are many possible ways to build a CPU that executes the RISC-V instruction set, depending on what trade-off you want in core size, power, speed, cost etc. Some such as Olof Kindgren’s award-winning “SERV” bit-serial FPGA core take several dozen clock cycles per instruction. Others such as SiFive’s superscalar 7-series and 8-series cores can execute on average more than one instruction per clock cycle.
In general, SiFive’s cores execute one instruction per clock cycle per pipeline, if a suitable instruction is available for dispatch, if required inputs are available. There can be delays if loads do not hit in cache or TIM, or if branches are mispredicted. You need to read the datasheet for the core you are interested in to get information, and even then only some cores in some specially-configured deterministic configurations produce guaranteed execution times.
RISC-V provides performance counter CSRs so that you can measure the number of instructions executed and number of clock cycles actually used by your code. SiFive cores can be configured to have additional performance monitoring counters such as cache misses, pipeline interlocks, branch mispredicts and so forth.
There is a chapter in our processor docs that gives pipeline info, though it doesn’t explain all of the details. You can find the processor docs at sifive.com/documentation
You can also find some info by looking at the gcc sources, in the pipeline description files, and the RTX_COST macros, but these are approximations of the hardware. See for instance https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/riscv/generic.md;h=fcd78b990feccbdceeee70df8de2cd1341757744;hb=HEAD
This is for rocket-chip which our 3 and 5 series parts are based on. There is also a sifive-7-series.md file. There is no pipeline description file for the 2 or 8 series parts yet.
Respected sir,
I have gone through the list of SiFive’s RISCV products. And found that Freedom U54 is based on RV64GC, which is of my concern.
Could you help me in this regard, for providing the base timing information of RV32GC for U54.
Thanks and Regards
Jim pointed you to the documentation.
The manual for the U54 is here
Section 3 has the information you want.
Thank you sir,
I have gone through the documentation of sifive u54.
But it contains the timing information of only RISCV base instructions. I want to know the number of cycles consumed for floating and compression instructions of RV32GC. Could anyone suggest me in this regard.
Hi Bruce,
I am looking for the most accurate way to measure the required cycles (time) for some applications I am benchmarking on the SiFive FE310-G002 available on the HiFive1 rev B. By looking at the Dhrystone, I found 3 different ways, but I am looking how to access, at C level not at assembly level, the performance counters. Can you point me to some useful information about this?
Best regards,
Jorge
Please see this C example for how to use the Hardware Performance Monitors:
Hi Jim,
thank you very much for pointing me to this file. Then I realized that the HPM support is available in other branch rather than in the default one (v201908-branch), which I was using. Now I am using the master and I was able to compile and run this example. However, I notice in this example-hpm that the METAL_HPM_CYCLE counter is read but never set and for that reason I always get 0 (zero). I put some additional dummy code and I was able to see changes in the other two counters set and read in this example-hpm.
What parameters should I use to proper set the METAL_HPM_CYCLE counter? I see the macros for events and classes in hpm.h, but I don’t know what they mean. Could please point me to additional documentation to better understand this.
Best regards,
Jorge