How to understand CSRs and find Cycles per Instruction?

HiFive Unleashed
1

Hi Everyone, I hope this is the right place to put my question. Because I did use any board.

I have a RISC-V Virtual Prototype and there are some softwares in it. I ran one of the software on RV32I and got the following report.
1, Are they CSRs?
2, Which information indicates the Cycles per Instruction?

the report I got:
Info: /OSCI/SystemC: Simulation stopped by user.
=[ core : 0 ]===========================
simulation time: 220580 ns
zero (x0) = 0
ra (x1) = 10238
sp (x2) = 1ffffec
gp (x3) = 21990
tp (x4) = 0
t0 (x5) = 2010000
t1 (x6) = 0
t2 (x7) = 1
s0/fp(x8) = 0
s1 (x9) = 0
a0 (x10) = 0
a1 (x11) = 0
a2 (x12) = 449
a3 (x13) = 0
a4 (x14) = 0
a5 (x15) = 0
a6 (x16) = 1
a7 (x17) = 5d
s2 (x18) = 0
s3 (x19) = 0
s4 (x20) = 0
s5 (x21) = 0
s6 (x22) = 0
s7 (x23) = 0
s8 (x24) = 0
s9 (x25) = 0
s10 (x26) = 0
s11 (x27) = 0
t3 (x28) = 0
t4 (x29) = 1
t5 (x30) = 8800
t6 (x31) = 5
pc = 101f4
num-instr = 6440

2

The x registers are the integer registers. There are no CSRs listed. There is no cycles per instruction info here. ISA Simulators normally don’t provide that info. You need something that simulators actual hardware, like a verilog processor description and a verilog simulator, to get cycles per instruction info. Or actual hardware.

This doesn’t look like a SiFive product. I suspect it is
[GitHub - agra-uni-bremen/riscv-vp: RISC-V Virtual Prototype](GitHub - agra-uni-bremen/riscv-vp: RISC-V Virtual Prototype
http://www.systemc-verification.org/
You should probably send questions to them.

3

Thank you Jim. It not a SiFive product. I did follow the link above.