Ask help: where to get accurate cycle number of each instruction on a specific RISC-V core?


(daiw) #1

Except memory load/store instruction, I think the cycle number of all others is determinate, right ?

I have most interest these cycle numbers on SiFive S51, U54, S7 and U7.

Thanks a lot.


(Bruce Hoult) #2

Only loads. Stores are 1 cycle from the point of view of the CPU.

Integer multiply and divide will always take the same amount of time for the same operand values (in the same order) on the same CPU, but can vary depending on operand value. There are also different options for size/speed tradeoffs in the multiplier and divider.

Floating point add/sub/mul/fma can start a new instruction every cycle with I think a four cycle latency. I think divide and square root can take variable amounts of time.

I believe a full description of the 7-series pipeline model and instruction dispatch rules has not been published. One detail that has been published is there is zero load-to-use delay, so code that is correctly scheduled for the 3 or 5 series with something else between the load and use is still correctly scheduled for the 7 series, despite dispatching two instructions per cycle.


(Jim Wilson) #3

At sifive.com/documentation you can find a Freedom U540 manual that has a section that describes the e51 execution pipeline and the u54 execution pipeline, pages 16 and 23 respectively. There is also similar info in the core complex manuals. We haven’t published docs for the 7-series yet as Bruce mentioned.


(daiw) #4

Thank you, Bruce and Jimw for your useful info.