Risc-v ipc

(bobzhang) #1
I recently is trying to measure riscv's ipc, I build riscv on xilinx zc706 board, debug it by openocd and gdb. my method is read csrs mcycle and minstret, but according to their value, riscv's lpc is about 0.25, not 1, anyone know the reason?

(Jim Wilson) #2

IPC will depend on which RISC-V core you are using, and what instructions you are executing. If you have a 64-bit core that produces one bit per cycle for integer divide with no early out, and then execute a divide, then that one instruction will take 64 cycles. There may also be issues relating to how many load/store instructions you are executing, and the speed of the memory system, which depends on whether your core has a cache or not. If no instruction cache and a 4 cycle access to instruction memory, then every instruction will take a minimum of 4 cycles. If you do have a fast instruction cache and only execute simple ALU instructions, and have a single-issue pipeline, then you should see an IPC of 1.

There could also be other issues relating to how mcycle and minstret are implemented. If your system has more than one clock, and mcycle is tied to a faster clock than the alu pipeline, then mcycle might be counting more than once for each alu pipeline cycle.

There are likely other explanations also.