What is the L2 Zero Device?

(CCelio) #1

The U54 MC manual contains a physical memory map with a chunk of memory devoted to the “L2 Zero Device”.

What is that? I didn’t see any other references in the manual for it.


(Drew) #2

Hi Chris,

We have an expanded the text in the Level 2 Cache Controller chapter and will be refreshing the public documents soon. I pasted an excerpt here for your convenience:

L2 Scratchpad

The SiFive L2 Cache Controller has a dedicated scratchpad address region which allows for allocation into the cache using an address range which is not memory backed.
This address region is denoted as the L2 Zero Device in the Memory Map in Chapter~\ref{chap:mmap}.
Writes to the scratchpad region will allocate into cache ways which are enabled and not masked.
Care must be taken with the scratchpad, however, as there is no memory backing this address space.
Cache evictions from addresses in the scratchpad will result in data loss.

The main advantage of the L2 Scratchpad over the L2-LIM is that it is a cacheable region allowing for data stored to the scratchpad to also be cached in a master’s L1 data cache resulting in faster access.

The recommended procedure for using the L2 Scratchpad is as follows:

  • Use the {\tt WayEnable} register to enable the desired cache ways.
  • Designate a single master which will allocate into the scratchpad. For this procedure we will designate this master Master S. All other masters will be denoted as Masters X.
  • Masters X: write to the {\tt WayMaskX} register to mask the ways which are to be used for the scratchpad.
    This will prevent Masters X from evicting cache lines in the designated scratchpad ways.
  • Master S: write to the {\tt WayMaskX} register to mask all ways except the ways which are to be used for the scratchpad. At this point Master S should only be able to allocate into the cache ways meant to be used as a scratchpad.
  • Master S: write scratchpad data into the L2 Scratchpad address range (L2 Zero Device).
  • Master S: Use the {\tt WayMaskX} register to mask the scratchpad ways for Master S so that it is no longer able to evict cache lines from the designated scratchpad ways.
  • At this point, the scratchpad ways should contain the scratchpad data, with all masters able to read, write, and execute from this address space, and no masters able to evict the scratchpad contents.