I’m not really experienced with cache coloring in general, so I’m asking here if more experienced people can give me some feedback.
Can anyone confirm me if it is possible to use cache coloring to do cache partionning on the HiFive Unleashed / FU540?
From my understanding :
Since the MMU is at the core level, so “before” the L2$, it seems totally possible to map the code in the DDR to only use the same cache lines of the L2$ and configure the MMU to remap all the code (through virtual addresses) as if it was a contiguous block.
Therefore, an application code can be executed as a single, contiguous block of code (from the PoV of the CPU), but the code is actually placed in DDR memory in such a way that the application will always use the same cache lines and no other application will use these cache lines. This would indeed create cache partionning between different applications running on the same or different cores.
(Side question : It also means the L2 is PIPT (Physically Indexed Physically Tagged), am I wrong?)
Therefore I think there is nothing preventing the use of cache coloring, but I may be wrong and totally misunderstand something.
Am I missing something ?