I develop for HiFive Unleashed board.
I have small question.
U54-MC-RVCoreIP.pdf Table 6.1
0x8000_0000 0xFFFF_FFFF RWXC Memory Port (cacheable?)
FU540-C000-v1.0.pdf Table 6
0x8000_0000 0x1F_FFFF_FFFF RWX A DDR Memory (none-cacheable?)
which one is correct?
The second. Although you don’t have this much DRAM attached.
HiFive Unleashed board have 8GB DDR4 on-board-memory.
Where is it mapped?
As above, starting at 0x8000_0000.
FYI the Hifive1 also has its 16 KB of SRAM mapped at 0x8000_000.
As conclusion,
Is on-board 8GB DDR4 memory non-cacheable?
I believe @terpstra was referring to the address range question and may have overlooked the parenthesised query about cacheability.
DRAM is cacheable. The cache wouldn’t get a lot of use otherwise 
OK.
Thank you for all.