DDR controller configuration register values for HiFive Unleashed


(Jonathan Neuschäfer) #1

Hi,

as part of porting coreboot to the HiFive Unleashed board, I would like to initialize the DDR RAM controller directly, rather than calling into FSBL. Section 20.3 of the FU540-C000 manual describes the sequence of that need to be performed, but it leaves out the values for the configuration registers at 0x100B0000-0x100B0424, 0x100B5200-0x100B52F8, and 0x100B4000-0x100B51FC, asking to “contact SiFive directly to determine the complete register settings for your application.”

I would like to know a set of register values that work on the HiFive Unleashed board, or a redistributable C/header file with these values, that could be included in a free software project such as coreboot.


(Bruce Hoult) #2

@mwachs5 @terpstra @palmer


(Wesley W. Terpstra) #3

While we’d love to provide you with this information, we believe we cannot. However, we can’t prevent anyone from disassembling the fsbl and copying the values sent to the blackbox DDR register map.


(Jonathan Neuschäfer) #4

Alright. Thank you for answering.


(Jasem Mutlaq) #6

And it didn’t take long for this to be featured at Phoronix: It Turns Out RISC-V Hardware So Far Isn’t Entirely Open-Source. I hope SiFive can explain more before rumors & FUD start spreading online turning this into a PR nightmare…


(Andrew Back) #7

I’m not quite sure how the advent of a free and open ISA plus implementations, gave way to an expectation that suddenly all the IP blocks you might require to build a practically useful SoC would be similarly free/open.


(Wesley W. Terpstra) #8

I saw a few posts on the internet, which misrepresented what I was expressing. I never suggested reverse engineering our partner’s IP!

SiFive is committed to supporting the open-source community. We are pleased to report that after discussions with our IP partners, we are now able to make available all the source code required to initialize the HiFive Unleashed board. The board’s boot sequence is described in the manual. The assembly code in the initial reset ROM is listed in the manual Chapter 6.1 “Reset Vector”. The firmware in the ZSBL mask ROM is directly readable by software on the chip, and we will be making the full source code available shortly. The source code for FSBL including the DDR initialization will also be available shortly. We can attest there is no other firmware run by the system during boot.


RISC-V openness controversy
(Bruce Hoult) #9

\o/


(Jeff Moe) #10

Just seeing this now, great news! And thanks for getting your upstreams to open up their code.


(Philipp Hug) #11

Any update on this?
Register values would be enough to help with the coreboot port.


#12

Any updates on this @terpstra? It’s been a couple months now.


(Wesley W. Terpstra) #13

Hopefully this has everything you need: