Does HiFive Unleashed have a DDR profile for OpenOCD debugging?

I have a question. When debugging HiFive Unleashed, it can directly link to the DDR address, so the DDR controller should be configured through the script first.I think there should be a configuration in openocd.cfg, but I can’t find it.

Hi liying,

The openocd.cfg script doesn’t initialize the DDR controller. The DDR controller gets initialized from the First Stage Boot Loader which runs on most boot configurations. If you can interrupt booting (at for instance the U-Boot prompt) you should be able to attach the debugger with the controller initialized.

If that’s not possible, what Mode Select value are you using?

Hi RalphF,
What you are talking about is that when the SoC starts up normally, the FSBL running in L2 RAM on the chip initializes the DDR, and then data and programs can be loaded into the DDR.What I mean is that when we use Freedom Studio OpenOCD or the JLink debugger, there is no bootloader to initialize DDR.JTAG loads the program directly to the DDR address 0x80000000.Theoretically, a script file is required to pre-initialize the DDR controller.For example, Xilinx SDK TCL, Ti CCS Gel script file will initialize DDR during debugging, but I can’t find such configuration file in Freedom Studio.

Hi liying,

We’re sorry but no stand-alone script was developed either.