Are there more in depth documentation on the specific implementation of the TileLink which interconnects the different cores (U54 and E51) on the U54-MC?
I can only find a few general information, but nothing more.
What I’m particularly interested in right now is if there is any mechanism avaiblable to limit the bandwidth (on the interconnect, either to L2 or to DDR) available for each core?
Does anyone have any idea regarding that? Or how it could be possible to do (if the TileLink doesn’t offer such a thing)?
The goal is to be able to limit the bandwidth of each core to mitigate the impact of interferences (at the interconnect level) when running applications on multiple cores.