Are there more in depth documentation on the specific implementation of the TileLink which interconnects the different cores (U54 and E51) on the U54-MC?
I can only find a few general information, but nothing more.
What I’m particularly interested in right now is if there is any mechanism avaiblable to limit the bandwidth (on the interconnect, either to L2 or to DDR) available for each core?
Does anyone have any idea regarding that? Or how it could be possible to do (if the TileLink doesn’t offer such a thing)?
The goal is to be able to limit the bandwidth of each core to mitigate the impact of interferences (at the interconnect level) when running applications on multiple cores.
I assume you mean you’ve read something like this:
You could implement the kind of bandwidth control capability you want in a crossbar module, and control it with a slave configuration agent in the same module. As seen at the end of section 2.1.
Or in the L2 cache module.
I don’t expect the standard U54-MC has any such capability, but I don’t know.
Indeed, I don’t think there is anything that would allow some kind of bandwidth control in the U54-MC unfortunately.
I’m just checking if someone has a more in-depth knowledge of the U54-MC regarding such a feature. @RalphF : Sorry to mention you here, but do you have any idea/quick answer?
Sorry, but none of our cores or memory interfaces provide bandwidth control. By design they operate as fast as possible. If you are trying to limit/restrict accesses to the L2 interface you’ll have to do this at the software level.