TileLink Performance Analysis

csk1153 (Chandra Katta) March 31, 2017, 2:35am 1

Do we have any details on TileLink Performance for various custom SoC usages?

Topic		Replies	Views
Tilelink GET operation General	1	1960	December 13, 2018
High core-to-core latency from c2clat benchmark HiFive Premier P550	2	251	February 14, 2026
ChipLink isn't an open spec, apparently, or can I see it somewhere? HiFive Unleashed	18	9620	June 7, 2019
Poor Dhrystone performance Freedom E300	53	13892	May 20, 2018
Compilation failure when TL_CLK of vcu118 is changed to 200 MHz Freedom U500	2	3027	April 14, 2020