I remain excited about RISCV and SiFive, in theory. I have the signed HiFive1 and HiFive Unleashed boards. I think I have all the published documentation. (and I’m pretty influential in the industry, after 50 years of contribution to systems architectural research and software product development).
So I’m also quite disappointed. I’d like to work on some hardware (communications, related to SDR and low level signalling/timing) and interface it to the HiFive Unleashed system. And it looks quite feasible.
But I’m running into what seems to be a problem with SiFive (maybe it’s just that they aren’t hiring the right staffing for this). Just as key register settings needed to use their product aren’t really “open” (apparenlty due to IP agreements, if I read their comments right), it seems like their hardware interfaces aren’t really open.
In this case, it is ChipLink. AFAICT, ChipLink is a physical embodiment (PHY) for TileLink. That’s great. There’s a draft spec for TileLink. But the word ChipLink does not appear in that document at all. In the FU540-C000 Manual (a good one, for the most part), it appears only in the block diagram and introduction as a named box.
Now, I have some pretty good experience with using signalling on the FMC interface to connect to cards. (The popular use for labs is the ZedBoard, MicroZed FMC carrier, and other places, and it’s used in a lot of AMC chassis. And ChipLink is carried on the FMC interface - that’s how it connects to HiFive Unleashed’s board from MicroSemi. But I don’t see that board as useful to me (and using Libero seems very expensive, too, even with a 1-year license built in the offer of the very expensive board for my needs.)
So, I’m stuck. I note that MicroSemi’s board doesn’t seem to contain any verilog or other support for the ChipLink in open (published form).
Am I missing something? Or is TileLink going to be open at an abstract level, but completely close and undocumented at the PHY level?
If so, I will stick with ARM. I don’t like ARM as much (especially it’s non-free aspect).
However, I would imagine that, if there is to be a useful community effort around RISCV and SiFive, locking up interfaces as proprietary and undocumented is a bad move.
I’d like to think that the slowness of release of the initialization register documentation (or even just Hex values) and the absence of ChipLink documentation is just arising from a tiny startup’s growing pains. If that is the case, please hire some developer support and start pushing out documentation and answering questions. We out here can help! And make some announcements (here on the forum, or in the press) about your roadmap and priorities.
Or, even better, just point us at the existing documentation (or even HDL source code)