The generated code (verilog) of ChipLink (io-fpga for vc707) HW block has missing signals on TileLink master and slave Interfaces. The missing signals are: (i) All B, C, E slave signals, (ii) data and error master signals of channel C.
So, I as far as I understand, theoretically the only possible TL-C (just the coherency subset of TL-C) transactions are:
a) Hi5Unleashed-2-VC707: Acquire and Release (except ReleaseData and ProbeAckData messages) only.
b) VC707-2-Hi5Unleashed: Probes only.
Am I wrong?