TileLink Interface of ChipLink HW FPGA block


(Antonis P.) #1

Hi,

The generated code (verilog) of ChipLink (io-fpga for vc707) HW block has missing signals on TileLink master and slave Interfaces. The missing signals are: (i) All B, C, E slave signals, (ii) data and error master signals of channel C.
So, I as far as I understand, theoretically the only possible TL-C (just the coherency subset of TL-C) transactions are:
a) Hi5Unleashed-2-VC707: Acquire and Release (except ReleaseData and ProbeAckData messages) only.
b) VC707-2-Hi5Unleashed: Probes only.

Am I wrong?


(Wesley W. Terpstra) #2

ChipLink supports all of the TileLink channels. However, in the iofpga design, there are no cache devices, so the generator optimizes away the unnecessary BCE channels. If you add cache slaves or masters to the design, the missing channels will reappear.


(Antonis P.) #3

Ok! Thks terpstra for the quick response!