Semi hosting using riscv openocd on SiFive board

I was trying to implement semihosting in a Nexys A7 board using a sample program with riscv-openocd with the Sifive toolchain. While debugging the board goes to exception at the first printf() line.
Using the command “monitor arm semihosting enable” seems to enable semihosting in openocd, but doesn’t produce printf output in the Debugger console.

Is riscv openocd supported in the Sifive boards? If there is, anywhere I could find a sample implementation of it?
Are there any additional code or libraries required for semi hosting to be implemented?

Liviu Ionescu’s gnu-mcu-eclipse has semihosting support.
SiFive is working on semihosting support now, and plan to make it available in a future toolchain release.

Meanwhile, Liviu’s semihosting patches are in openocd that you already found. Keith Packard of SiFive has qemu semihosting patches that have been posted upstream but not accepted yet, they asked for a formal spec first. So there should be someone working on a formal proposal for RISC-V semihosting support based on Liviu’s work maybe as part of the debug spec, but I’m not part of that discussion.

I haven’t used the semihosting support, but as far as I know it works the same as the arm semihosting support.

This is the expected behaviour when using the SiFive toolchain, because it automatically adds libgloss to your application, and then RISC-V libgloss terminates all system calls with ECALLs, expecting someone to handle them, which cannot happen for regular bare-metal applications.

You need a toolchain that does not add libgloss (like the xPack RISC-V GCC) and you have to implement the low level newlib functions to use the semihosting API instead of ECALLs. You can find such an implementation in the projects generated by the GNU MCU Eclipse - SiFive Templates.

Semihosting support was added to OpenOCD a while ago; you can find the very latest binaries at Release Test binaries · xpack-dev-tools/pre-releases · GitHub (the public release will be available soon)