I’m also considering adding semihosting support for RISC-V projects in GNU MCU Eclipse, but unfortunately I did not find a reasonable way to implement it.
Traditionally, semihosting calls use a reserved debugger break; on Cortex-M this is (if I remember right) BKPT 0xAB; (BKPT has a byte where various values can be passed to the debugger).
On RISC-V, with its very tight instruction encoding, there is only one BREAK instruction, which should be preserved as a way for the application to break to the debugger. So there is no easy way to implement a specific break to the debugger, that can be used to implement the semihosting call.
I was thinking on a workaround, for example to use a sequence of instructions together with placing a magic number in a register; my preference would be something like EBREAK & NOP, and a vallue like 0xca11ab1e (callable); the purpose is to minimise the risc of entering a semihosting call from a normal break.
Time permitting, I’ll try to implement this in OpenOCD and add suport for semihosting in the projects generate by the future SiFive Eclipse project template.