A wish: Simplified flash tool for HiFive1


(Matthias Koch) #1

I have a wish:
I would like a simplified flash tool just to read and write the contents of flash memory on a HiFive1.

The idea is: With Mecrisp-Quintus, I have a complete Forth environment working inside the chip, so there is no need for debugging capabilities. But flashing the board on a different computer always requires the installation of OpenOCD and GDB, which is a lenghty process.

Why not have a simple tool, working with libusb, easily compileable and with as few external dependencies as possible, to take care of flashing ?

Just for reference, the stm32loader is doing exactly what I want, but for another chip family:

If you have a pointer for me on how to flash the HiFive1 with OpenOCD alone, I would be glad, too.

Matthias


(Penguin) #2

By “with OpenOCD alone” do you mean without gdb? (Because I don’t think thats possible?)

Since the HiFive1 is fairly new, you could always look into developing some scripts to do this with gdb and openocd. I plan on doing this once I get a HiFive1.


(Matthias Koch) #3

Yes, I mean without GDB. Thank you for the motivation - I tried myself. Here comes my OpenOCD script which you can run with the binary OpenOCD supplied by SiFive. Launch with openocd -f openocd.cfg
You just have to specify your binary file name in the config file before use.

adapter_khz     10000

interface ftdi
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010

ftdi_layout_init 0x0008 0x001b
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020

#Reset Stretcher logic on FE310 is ~1 second long
#This doesn't apply if you use
# ftdi_set_signal, but still good to document
#adapter_nsrst_delay 1500

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1

flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
#reset -- This type of reset is not implemented yet
if {[ info exists pulse_srst]} {
  ftdi_set_signal nSRST 0
  ftdi_set_signal nSRST z
  #Wait for the reset stretcher
  #It will work without this, but
  #will incur lots of delays for later commands.
  sleep 1500
}
halt
flash protect 0 64 last off

flash write_image erase mecrisp-quintus-hifive1-with-disassembler.bin 0x20400000

shutdown

#4

hi,
I’ve developed the development system for Mecrisp-Quintus 0.10 for RISC-V 32 IM on HiFive1 by Matthias Koch. Hope it can ease the programming of RISC-V mecrispForth.
It include the following items. For now I can simulate the RISC-V RV32I and RV32M instruction set and run tinyForth(tF) as the helping hand to debug the instructions as well as simulating mecrispForth without having to have hardware at hand.
( 5 ) RISC-V-TF87.F
( 4 ) RISC-V-hifive87org.f
( 3 ) RISC-V-SIMULATOR87.F
( 2 ) RISC-V-DISASSEMBLER87.F
( 1 ) RISC-V-ASSEMBLER87.F
cur-file --> D:\WIN32FOR\RISC-V88.F

I’d like to share this development system with people if they’d like.
May Forth be with you! holi

partial of the decompiled and disassembled list:
\ *******************************************************************************
\ *******************************************************************************
( 20400004 2040002C )
( 20400008 FFFFFFFF )
\ 2040000C 1C 2D 2D 2D 20 4D 65 63 72 69 73 70 2D 51 75 69 6E 74 75 73 20 30 2E 31 30 20 2D 2D 2D
\ ------------------------------------------------------------------------------- ( 1 1 )
code — Mecrisp-Quintus 0.10 —
( 2040002C 50 00 40 20 )

\ *******************************************************************************
\ *******************************************************************************
( 2040002C 20400050 )
( 20400030 00000042 )
\ 20400034 04 32 64 75 70
\ ------------------------------------------------------------------------------- ( 2 2 )
code 2dup
( 2040003C 00022283 ) R5=(R4+0)
( 20400040 FF820213 ) R4-8
( 20400044 00322223 ) (R4+4)=R3
( 20400048 00522023 ) (R4+0)=R5
( 2040004C 00008067 ) ret
\ -------------------------------------------------------------------------------

\ *******************************************************************************
\ *******************************************************************************
( 20400050 2040006C )
( 20400054 00000062 )
\ 20400058 05 32 64 72 6F 70
\ ------------------------------------------------------------------------------- ( 3 3 )
code 2drop
( 20400060 00422183 ) R3=(R4+4)
( 20400064 00820213 ) R4+8
( 20400068 00008067 ) ret
\ -------------------------------------------------------------------------------

\ *******************************************************************************
\ *******************************************************************************
( 2040006C 2040009C )
( 20400070 00000044 )
\ 20400074 05 32 73 77 61 70
\ ------------------------------------------------------------------------------- ( 4 4 )
code 2swap
( 2040007C 00018293 ) R5=R3+0
( 20400080 00422183 ) R3=(R4+4)
( 20400084 00522223 ) (R4+4)=R5
( 20400088 00022283 ) R5=(R4+0)
( 2040008C 00822303 ) R6=(R4+8)
( 20400090 00522423 ) (R4+8)=R5
( 20400094 00622023 ) (R4+0)=R6
( 20400098 00008067 ) ret

        \ ------------------------------------------------------------------------------- (      305      131 )
                               code  quit

( 20405CC8 80000137 46810113 ) R2=80000468
( 20405CD0 80000237 26820213 ) R4=80000268
( 20405CD8 934FC0EF ) initflash \ 7E 20401E0C
( 20405CDC 80004337 FF030313 ) R6=80003FF0
( 20405CE4 00A00293 ) addi_R5,R0,0A
( 20405CE8 00532023 ) sw_R5,R6,0
( 20405CEC 80004337 FC830313 ) R6=80003FC8
( 20405CF4 00000293 ) addi_R5,R0,0
( 20405CF8 00532023 ) sw_R5,R6,0
( 20405CFC 80000337 00830313 ) R6=80000008
( 20405D04 00000293 ) addi_R5,R0,0
( 20405D08 00532023 ) sw_R5,R6,0
( 20405D0C 80004337 FD430313 ) R6=80003FD4
( 20405D14 00000293 ) addi_R5,R0,0
( 20405D18 00532023 ) sw_R5,R6,0
( 20405D1C 80004337 FCC30313 ) R6=80003FCC
( 20405D24 00000293 ) addi_R5,R0,0
( 20405D28 00532023 ) sw_R5,R6,0
( 20405D2C 800002B7 46828293 ) R5=80000468
( 20405D34 00532223 ) sw_R5,R6,4
( 20405D38 800042B7 FC428293 ) R5=80003FC4
( 20405D40 0002A283 ) lw_R5,[R5+0]
( 20405D44 00000293 ) addi_R5,R0,0
( 20405D48 B01FC0EF ) query \ B3 20402848
( 20405D4C D05FF0EF ) interpret \ 12F 20405A50
( 20405D50 D81FC0EF 05 20 6F 6B 2E 0A )
." ok."
( 20405D5C FEDFF06F ) jmp_20405D48


(Matthias Koch) #5

Hello Holi,

some time ago I received disassembled parts of Mecrisp-Quintus in a special syntax, I remember. Could you please explain in a few sentences what tinyForth (tF) does ? I am especially interested in the RISC-V assembler and simulator written in Forth itself, which should allow to single-step through definitions on the target hardware itself, as my RISC-V simulator Mamihlapinatapai is written in ARM assembler. Where can I find your source code ?

Matthias


(Tommy Murphy) #6

Do you really need to embed the filename in the script?
Can’t you do something like:

openocd -f openocd.cfg -c "flash write_image erase mecrisp-quintus-hifive1-with-disassembler.bin 0x20400000"

In fact can’t you just use the existing (?) openocd configuration script rather than a “special” one named openocd.cfg?

Admittedly I haven’t tried this with the HiFive1 board myself (yet) but something along those lines should work I think…


(Matthias Koch) #7

Sure, but I need to write the same binary file every time, so it’s convenient for me. I just could not find the OpenOCD way of flashing the HiFive1 without GDB documented anywhere else, therefore I posted it here.


#8

hi, Matthias
I’m so glad to receive the reply from you. I can almost simulate the mecrispForth for risc-v 32IM. The cross-compiler under win32for 4.2.67x can well do the assembling and disassembling of RISC-v instruction set. It can run tF ( tinyForth) as well as mecrispForth, while tF being part of MecrispForth. But tF is simpler and faster as far as simulator is concerned. I’d like to promote Algebraic Assembler eagerly, as you can see in the dis-assembler list. One thing worth mentioned is that the dis-assembler can be generated automatically while compiling assembler not to mention simulator
. As for tinyforth it is nothing but very simple like this:
t: tF push.R1 hex rp=80000468 sp=80000268
begin’ cr KEY EXECUTE.COMMAND(TF)
again’ pop.R1 RET
You can see the complete source code here at:
https://groups.yahoo.com/neo/groups/armForth/files/RISC-v%20/


(Matthias Koch) #9

Dear Holi,

actually, I cannot see anything at the link you provided without being a registered user there. Could you please put the files into a public place or send them to me via E-Mail ?

Matthias


#10

Another Forth enthusiast here. I’ve got my own system - muforth - that I’m using to write code for RISC-V.

While I don’t have an exact solution to your request - I have not yet implemented the code to program the SPI flash on the HiFive1, I have implemented - in Forth - code that talks to the openocd “gdb server”. I’ve used this to explore the chip (I’ve got an interactive memory dumper and disassembler) and to write a simple ITC Forth into the RAM (DTIM) and execute words there.

Using something like my Forth code to talk to openocd would get you closer to your goal.

You might be interested in checking it out!

There’s a muforth Github repo and also a (very incomplete) muforth web site, but the web site does have a few pages devoted to RISC-V.

The mu/target/RISC-V directory in the Github project is probably going to be the most interesting to you.

Good luck!

  • David

#11

I didn’t read through the thread carefully enough to realize that you had figured out how to flash using a command to openocd. I didn’t realize it was that easy. :wink:

I still think you should check out muforth.


(Matthias Koch) #12

Thank you, David ! I wrote an E-Mail to your webhamster… address. Matthias