Hello, trying to get riscv-rust-quickstart to work with Hifive1 Rev B, but having trouble. Tried platform io, but Rust support doesn’t seem there. Instead, tried to use openocd, but had trouble there too; seems like SiFive prebuilt binary predate commit used to facilitate openocd cfg. Suggested post here since openocd fork and SiFive can be out of sync, but really just trying to get cargo run --example leds_blink
to work. If anyone has any ideas please advise.
Not sure about the first issue, but for openocd support: yes the prebuilt lacks support for it and you’ll need to build riscv/riscv-openocd from at least the commit that added the config (https://github.com/riscv/riscv-openocd/commit/548790fefc5da04a2a60d6fb54f765c7bf959e42)
Note: looking at comments on that commit and appears there are different pids for different boards that still don’t fix this entirely… You may want to check with lsusb to see what yours shows up as.
Okay thank you this is helpful. Will rebuild with new pid, and let you know if that gets it to work.
Think the first issue is probably more relevant though since that seems to be the recommended method to build. If anyone more familiar with JLink knows how to fix Waiting for GDB connection...
on LinkGDBServer -device FE310 -if JTAG -speed 4000 -port 3333 -nogui
, please advise. Alternative, if anyone knows an easier way to get started with rust on Hifive1 Rev B, very open to suggestions
Turns out rebuilding with new pid resolved. Thank you very much!
Huzzah! Glad that worked out!
Would you be willing to post that as an issue on the repo as well, with your pid/board?
Sure would be happy to do so!
Unfortunately I am now running into another issue that appears to be related to one you saw earlier where I get ERROR: first sector must be <= last.
I am now trying to flash something a bit more substantial than just those from the quickstart linked above (eventually hoping to port new RTOS, which currently only supports HiFive1), so am unsure if it’s related to your post/the original issue.
Would you prefer to wait on filing the issue, or just go ahead with potentially limited scope?
That error should be a false alarm. Have you been able to flash programs otherwise?
My last post in that thread shows the correct line we should be using, but I also noticed the flash on my RevBs were already unlocked and flashable. You should be able to see this is the case if you start openocd manually, connect through gdb, and run monitor flash info 0
I say go ahead and file the pid/board issue since that should be its own thing (and good way to get visibility to that comment on github)
To be honest, not totally sure. Am able to get output from serial, but am still trying to understand some basic examples involving UART and SPI. Think it is possible need to configure PMP registers for userspace application isolation in advance examples.
Have a basic write-up ready (see below), but posting here first since don’t want to annoy people by not just posting PR (esp. since another user already raised similar issue). If you think it okay will post
Writeup for riscv-openocd #471
Hifive1b Missing pid resolution
This issue is just to document a problem and solution to previous issue as requested. SiFive prebuilt binary predate commit used to facilitate openocd cfg. So it’s necessary to build riscv-openocd from this repo, but as mentioned openocd misses board pid. This also caused problems building some of the quickstart riscv libraries which relied on openocd (originally did not know issue was openocd).
Following commit, resolve issue as follows:
- lsusb
Use lsusb to find proper pid
- update contrib/60-openocd.rules
ATTRS{idVendor}==“1366”, ATTRS{idProduct}==“<YOURPID>”, MODE=“660”, GROUP=“plugdev”, TAG+=“uaccess”
- update src/jtag/drivers/libjaylink/contrib/99-libjaylink.rules
{0x<YOURPID>, 0},
- update tcl/board/sifive-hifive1-revb.cfg
#flash protect 0 64 last of
Original solution here is from @KendiMedAmine and question about why is raised here.
I’m actually newer here as well and still learning but, riacv-openocd is pretty active/responsive so that should be fine to post.